`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:05:50 07/06/2014 
// Design Name: 
// Module Name:    mod_7_6bit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mod_7_6bit(
    input [5:0] in,
	 output reg [2:0] out
    );

always@(in)
case(in)
	0: out = 0;
	1: out = 1;
	2: out = 2;
	3: out = 3;
	4: out = 4;
	5: out = 5;
	6: out = 6;
	7: out = 0;
	8: out = 1;
	9: out = 2;
	10: out = 3;
	11: out = 4;
	12: out = 5;
	13: out = 6;
	14: out = 0;
	15: out = 1;
	16: out = 2;
	17: out = 3;
	18: out = 4;
	19: out = 5;
	20: out = 6;
	21: out = 0;
	22: out = 1;
	23: out = 2;
	24: out = 3;
	25: out = 4;
	26: out = 5;
	27: out = 6;
	28: out = 0;
	29: out = 1;
	30: out = 2;
	31: out = 3;
	32: out = 4;
	33: out = 5;
	34: out = 6;
	35: out = 0;
	36: out = 1;
	37: out = 2;
	38: out = 3;
	39: out = 4;
	40: out = 5;
	41: out = 6;
	42: out = 0;
	43: out = 1;
	44: out = 2;
	45: out = 3;
	46: out = 4;
	47: out = 5;
	48: out = 6;
	49: out = 0;
	50: out = 1;
	51: out = 2;
	52: out = 3;
	53: out = 4;
	54: out = 5;
	55: out = 6;
	56: out = 0;
	57: out = 1;
	58: out = 2;
	59: out = 3;
	60: out = 4;
	61: out = 5;
	62: out = 6;
	63: out = 0;
endcase

endmodule
